1. Field of the Invention
The present invention generally relates to a semiconductor device and a control method for reading instructions, and more particularly to a system-in-package semiconductor device using a rewritable non-volatile memory and a control method for reading instructions in such a semiconductor device.
2. Background Art
In recent years, many rewritable non-volatile memories (e.g., flash memories) have been installed in an electronic circuit system. Flash memories are mainly classified into a NAND type and a NOR type. Typically, a NAND flash memory is suitable for dealing with a large volume of data because of large capacity and thus NAND flash memory is inexpensive in terms of price per bit, but it requires a controller and a RAM for shadowing, resulting in likely making a circuit configuration complicated. In contrast, although a NOR flash memory has small capacity and operates at a relatively lower speed, it is suitable for storing program codes (instruction codes) and firmware because of simple circuit configuration, and therefore there is also provided the specifications called XiP (eXecute-in-Place).
In general, a NOR flash memory includes a parallel type and a serial type. A NOR serial flash memory has a small number of pins and thus can achieve reduction in chip area, thereby enabling cost saving for implementation of a board. Therefore, the NOR serial flash memory, among others, and a system-in-package (SIP), in which such a memory is installed together with a CPU, is expected to be utilized in the future.
In addition, improvement of an operation speed of an electronic circuit system is constantly requested, and various techniques for improving such an operation speed have been proposed.
Japanese Patent Publication No. 2010-146142 (hereinafter the “publication”) discloses a technique of reducing a time required for activating a program, such as an OS (operating system) in an information processing apparatus. Specifically, the publication discloses an information processing apparatus having two processors, namely: a first processor which reads out a plurality of instructions relating to the OS from a DRAM to execute preparation processing for enabling the OS to be executed (e.g., consistency check of kernel images held in the DRAM), a second processor which reads out a plurality of instructions relating to the OS from a flash memory and executes the instructions temporally parallel with execution of the preparation processing of the first processor, and further which switches a source of obtaining the instructions relating to the OS from the flash memory to the DRAM in response to completion of the preparation processing in order to continuously execute the OS.
In such conventional information processing apparatus disclosed in the publication as discussed above, a DRAM is used to store the instructions relating to the OS. Accordingly, it is necessary to make a circuit design taking into account wiring lines in accordance with a number of pins provided at the DRAM, and thus it is difficult to achieve a chip downsizing. That is, such an information processing apparatus is designed under the system policy, which enables use of a large-capacity, higher-speed DRAM in accordance with an increase of kernel image size as a result of the OS having higher functions, and thus such an information processing apparatus is unsuitable for a system environment in which a DRAM cannot be used or in which reduction in chip implementation area is strongly desired.
A NOR flash memory is often used to store instruction codes in a system environment, in which high reliability is desired because of its characteristics, and in which a technique for further improving a read-out speed has been desired. In this regard, a NOR serial flash memory is a promising memory which largely contributes to reduction in chip area because of a small number of I/O pins; however, as its read-out speed is lower than other flash memories, in a case where the NOR serial flash memory is installed in a system-in-package semiconductor device, the read-out speed becomes a bottleneck. In particular, when a CPU reads out an instruction regarding a branch from the NOR serial flash memory in order to execute the instruction, waiting occurs on the CPU because of its structure until read-out from the NOR serial flash memory is ready, and as a result of this, performance of the CPU deteriorates. In other words, with the NOR serial flash memory, if there is continuity between read-out addresses, data can be read out at a relatively high speed, whereas if there is no continuity between read-out addresses (e.g., there is an address jump by a branch instruction, a jump instruction, etc.), an overhead occurs during processing from when an address is designated until data is read out, disadvantageously causing the CPU to be held in abeyance during that period.